Honored Contributor
Honored ContributorI am not sure that you can use frame locking without clock locking. It is likely that your input and output clocks are physically different. Even if they have the same advertised clock rate they will drift apart and I am not sure how the CVO and your output will cope with that. I believe the output stream will be unstable.
You will not be able to tie the SOF signals with Nios. This is better done in the top-level HDL file. The SOF signals are exported by the Qsys/SOPCBuilder system. --- Quote Start --- Hi, i read at the ug_vip.pdf, that I need a VCXO to do GenLock (Clock Locking). But I think my Board (Altera Cyclone III Development Board) don't have a VCXO. But do you think its possible to use Frame Locking instead of Clock Locking? I looked this training video from altera: http://www.altera.com/customertraining/webex/implementing_video_systems/player.html And it seems that I only have to tie the input and output SOF signal, like you and gwall said before, to use Frame Locking. If I can do so, is it correct that this could do it in NiosII: while (1) { cvo_1(sof) = cvi_1(sof); cvo_2(sof) = cvi_1(sof); cvo_3(sof) = cvi_1(sof); ... } Thank you! --- Quote End ---
