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Hi,
Assuming I understood this correctly, the issue you are having is that the outputs from the CVOs are not synchronized.
The user guide has a few sections about generator lock and aligning the CVO output to an incoming start_of_frame signal. Is it something that can be used to fix your problem?
Edit: As gwall pointed out, you will also have to tie the output clock and the output SOF signal to the input clock and the input SOF signal.
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Hi,
i read at the ug_vip.pdf, that I need a VCXO to do GenLock (Clock Locking). But I think my Board (Altera Cyclone III Development Board) don't have a VCXO.
But do you think its possible to use Frame Locking instead of Clock Locking? I looked this training video from altera:
http://www.altera.com/customertraining/webex/implementing_video_systems/player.html And it seems that I only have to tie the input and output SOF signal, like you and gwall said before, to use Frame Locking.
If I can do so, is it correct that this could do it in NiosII:
while (1)
{
cvo_1(sof) = cvi_1(sof);
cvo_2(sof) = cvi_1(sof);
cvo_3(sof) = cvi_1(sof);
...
}
Thank you!
Honored Contributor
