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Are your four video inputs to the FPGA synchronized to each other?
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The inputs are the same at each CVI, I splitted the source signal out of the SOPC Builder.
Input => SOPC System => Self Programmed Mixer => Output
SOPC System:
CVI - Clipper - FrameBuffer - Scaler - CVO
CVI - Clipper - FrameBuffer - Scaler - CVO
CVI - Clipper - FrameBuffer - Scaler - CVO
I clipped different parts of the video and have scaled them up.
If I clipp always the same parts of a videostream, I get only an offset of a few pixels, which I can compensate by a self written Verilog code.
But when I clipp different parts, i get an offset of around ~50% of all lines
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