Verilog .v and.vp on zip file to Qsys

Question

I got a model in Verilog from my development board's SDRAM controller controller manufacturer. The model comes in a file. zip that contains a file. .vp and a .vp file. How to convert to an Qsys component?

dicas3d · Answer

I think that I need to use modelsim or another simulation software to do the task. Can anyone who knows confirm? I don't tryed yet because just on Monday I have access to the computer with the Quartus prime lite and the project that I'm working.

syafieqs · Answer

You issue seem to be related to the encryption.

You may look into below link for detail.

There is discussion on encrypted Verilog.

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Decrypt-verilog-file/td-p/1383551

dicas3d · Answer

Yes, maybe. But in my particular case I even don't know if I need any key and I'm in doubt if I'm capable of working with the model without NC-Verilog because it's payed. To check it better the model is the provided in link https://www.winbond.com/hq/product/specialty-dram/sdram/?__locale=en&amp;partNo=W9864G6JT . Does Intel Quartus Prime Lite allow precompiled Verilog models to be used as components? If yes, I can try compiling on edaplayground which has NC-Verilog.

fvm · Answer

Hello,not completely clear what you are trying to achieve. The RAM model is for simulation only. Typically you connect it in the simulation top level (test bench) to your design under test.

dicas3d · Answer

From what I've researched so far there is no ready IP Core available for QSYS for this SDRAM controller. What I'm trying to do is to solve this. Even the manufacturer sends this when asked about it. So what I'm trying to do is use the model as/convert the model to the IP Core. As I know in Quartus Prime pro we can execute simulation models inside a component to do it called Generic Component.

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Verilog .v and.vp on zip file to Qsys

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