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dicas3d's avatar
dicas3d
Icon for New Contributor rankNew Contributor
2 years ago

Verilog .v and.vp on zip file to Qsys

I got a model in Verilog from my development board's SDRAM controller controller manufacturer. The model comes in a file. zip that contains a file. .vp and a .vp file. How to convert to an Qsys compon...
Memory
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
Hello,
not completely clear what you are trying to achieve. The RAM model is for simulation only. Typically you connect it in the simulation top level (test bench) to your design under test.
  • dicas3d's avatar
    dicas3d
    Icon for New Contributor rankNew Contributor
    2 years ago

    From what I've researched so far there is no ready IP Core available for QSYS for this SDRAM controller. What I'm trying to do is to solve this. Even the manufacturer sends this when asked about it. So what I'm trying to do is use the model as/convert the model to the IP Core. As I know in Quartus Prime pro we can execute simulation models inside a component to do it called Generic Component.