Verilog .v and.vp on zip file to Qsys

Yes, maybe. But in my particular case I even don't know if I need any key and I'm in doubt if I'm capable of working with the model without NC-Verilog because it's payed. To check it better the model is the provided in link https://www.winbond.com/hq/product/specialty-dram/sdram/?__locale=en&partNo=W9864G6JT . Does Intel Quartus Prime Lite allow precompiled Verilog models to be used as components? If yes, I can try compiling on edaplayground which has NC-Verilog.