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dicas3d's avatar
dicas3d
Icon for New Contributor rankNew Contributor
2 years ago

Verilog .v and.vp on zip file to Qsys

I got a model in Verilog from my development board's SDRAM controller controller manufacturer. The model comes in a file. zip that contains a file. .vp and a .vp file. How to convert to an Qsys compon...
Memory
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
2 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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