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Peter01's avatar
Peter01
Icon for New Contributor rankNew Contributor
2 years ago

Use case of SLD hub controller

I want to use SLD hub in MAX-V FPGA.

The sink of SLD hub would be SLD node in the FPGA fabric.

How about the source of SLD hub ? , what is it's input ? (channel and protocol).

9 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor

    Hi,
    sld_hub_controller is used as lower level interface in sld_hub_controller_system and jtag-over-protocol IP, which are the hardware interfaces of documented remote debug solutions, see AN693 and AN971. The interfaces and protocols are not documented as such.

    altera_streaming_sld_hub_controller_core.sv source has however meaningful comments, variable and state names, it's not too difficult to understand the intended usage. A testbench can help to figure out control timing.


    MAX V has limited debugging capabilities due to low LE count, which debugging functions are you looking for?

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor

    You may refer to this diagram :

    regards,
    Farabi

  • Peter01's avatar
    Peter01
    Icon for New Contributor rankNew Contributor

    Hi Farabi,

    I have look the diagram.

    Its from AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC.

    How the SoC can be replaced with the FPGA to debug over TCP/IP.

    I want to debug the MAX-V FPGA.

    thank you.

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      Don't understand why you rely on using MAX V for the project. It has no on-chip RAM and can't implement Signaltap.

      There's a principle option to implement hardware TCP/IP stack in FPGA (probably needing more logic cells than provided by MAX V), but it's not supported by any Intel IP.

      A processor-less remote debug interface can be easier implemented through other fast serial links.
      • Peter01's avatar
        Peter01
        Icon for New Contributor rankNew Contributor

        Hi Frank,

        I can replace MAX V with MAX10.

        *************

        There's a principle option to implement hardware TCP/IP stack in FPGA (probably needing more logic cells than provided by MAX V), but it's not supported by any Intel IP.

        I have planned this initially but dropped due to complexity.

        *************

        A processor-less remote debug interface can be easier implemented through other fast serial links.
        This exactly suits my application . Could you provide suggestion to remote debug (signaltap) .
        I am aware of using JTAGD (Linux JTAG server) on x86 platform and using USB blaster. But this doesn't fit in my requirement.
        A hint on use of SLD hub controller for remote debug would be appreciated.
        Thank you.
  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor

    Hello,


    Do you have further request?


    regards,

    Farabi


  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor

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