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Peter01's avatar
Peter01
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2 years ago

Use case of SLD hub controller

I want to use SLD hub in MAX-V FPGA. The sink of SLD hub would be SLD node in the FPGA fabric. How about the source of SLD hub ? , what is it's input ? (channel and protocol).
Ethernet
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
Don't understand why you rely on using MAX V for the project. It has no on-chip RAM and can't implement Signaltap.

There's a principle option to implement hardware TCP/IP stack in FPGA (probably needing more logic cells than provided by MAX V), but it's not supported by any Intel IP.

A processor-less remote debug interface can be easier implemented through other fast serial links.
Peter01's avatar
Peter01
Icon for New Contributor rankNew Contributor
2 years ago

Hi Frank,

I can replace MAX V with MAX10.

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There's a principle option to implement hardware TCP/IP stack in FPGA (probably needing more logic cells than provided by MAX V), but it's not supported by any Intel IP.

I have planned this initially but dropped due to complexity.

*************

A processor-less remote debug interface can be easier implemented through other fast serial links.
This exactly suits my application . Could you provide suggestion to remote debug (signaltap) .
I am aware of using JTAGD (Linux JTAG server) on x86 platform and using USB blaster. But this doesn't fit in my requirement.
A hint on use of SLD hub controller for remote debug would be appreciated.
Thank you.