Peter01New Contributor2 years agoUse case of SLD hub controller I want to use SLD hub in MAX-V FPGA. The sink of SLD hub would be SLD node in the FPGA fabric. How about the source of SLD hub ? , what is it's input ? (channel and protocol).
FarabiRegular Contributor to Farabi2 years agolink : https://www.intel.com/content/www/us/en/docs/programmable/723698/current/supported-system-debugging-tools.htmlregards,Farabi
Recent DiscussionsConfigurable transceiver enableF-Tile Ethernet Hard IP Design Example - TestbenchF-tile-ethernet-hard-ip TX/RX MAC Segmented Client InterfaceF-tile 10GBASE-R firecode FEC IP (Agilex 7)Inquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5