Honored ContributorCan anyone say why ?
I have a single EP design using Avalon MM interconnect and across Cyclone IV, Arria V and Stratix V and I want to support Gen3 X1, X4 and X8 on the Stratix V card ... This is a problem to switch to Avalon ST interconnect for one design point .... Any ideas on how to get around this ? Thanks, Bob.
Honored ContributorIf you use the Reference Design Gen3x8 AVMM 256-bit DMA for External DDR3 - Stratix V at http://www.alterawiki.com/wiki/refer...r3_-_stratix_v,
it should works out of the box. Ensure you have reboot the PC after programmed the .sof into FPGA for the PCIe link to establish.Honored ContributorRegarding the simulation error, refer to solution:
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04092014_108.htmlHonored ContributorThank you. That is going to work.
How about the previous question.Honored ContributorI assume your previous question is below:
"I have compiled it as a TOP (with success) and programmed the final sof to a Stratix V PCIe Gen3x8 based board, but I could not get the thing to work (not even "lspci" could recognize the board at start up)." The Gen3_x8_AVMM_256-bit_DMA_for_External_DDR3_-_Stratix_V example design had been tested, it should works out of the box.Honored ContributorFor your information, there is one set of DIP switch (SW6) on Stratix V dev kit related to PCIe and that is to select the lane width.
Ensure you have set the DIP switches to factory default settings. Refer to Figure 4-2 of 'Stratix V GX FPGA Development Kit User Guide' at https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_svgx_fpga_dev_kit.pdfHonored ContributorHonored ContributorMake sure you make changes to the pins. The GX version is different from the GS version. I have tested this design in a GS chip and works fine. You might want to try the design first without the DDR3 since thats another challenge.
-TrukngHonored ContributorThe issue I have now is that the Stratix V example designs for Gen3x4 or Gen3x8 use a DMA controller and a 64 bit address on the TXS ... I have Cyclone and Arria designs that use NIOS to connect to the TXS port using the CRA translation table configured via NIOS II .
I am not sure how to port the design to Stratix for Gen3x4 or Gen3x8 ... I am currently telling QSYS that the TXS port width is 20 bits and running the Generate to get the Verilog RTL. I then altering the TXS width parameter to 64 bits and concatenating the upper 44 bits to the address into the TXS slave as a hard wired NIOS address -> 64 bit PCIe address translation. Any other ideas on how to port the original design ?Honored ContributorCan any one say how I get the CRA tables to support dynamic A2P address translation into a Stratix V gen3x4 or gen3x8 design ... I can only think that I can look at how it is implemented in Cyclone and Arria V and then see how to convert to Stratix V .
Honored ContributorSo I moved to the gen3x4 design and added NIOS II and some On Chip Memory ... the card works fine so far except for the gen3_led doesn't com on ... when in a gen3 slot the configuration link status indicates a 0x43 which is gen3x4 ... but no gen3_led only the L0_led and the four link leds are on indicating x4 and alive_led flashing ... tomorrow I will confirm gen3x4 operation by adding an analyzer. Almost identical designs that are gen3x8 have the same top_hw.v design where all the LED's are decoded .. the gen3_led is decoded off
assign gen3_speed = tl_cfg_tl_cfg_sts[32:31] == 2'b11; I would like to find the documentation on tl_cfg_tl_cfg_sts but other elements of it like the link width appear to work. With the simulation Generation flipping out on me .... (see the other thread) I am stuck. This vector is generated by altpcie_sv_hip_ast_hip_status_bridge ... that I can't find anything on either. I guess I will try the PCIe ug from Altera. Thanks, Bob.
