Stratix V PCIe HIP not supporting Avalon MM Gen3 x8 I/F

The issue I have now is that the Stratix V example designs for Gen3x4 or Gen3x8 use a DMA controller and a 64 bit address on the TXS ... I have Cyclone and Arria designs that use NIOS to connect to the TXS port using the CRA translation table configured via NIOS II .

I am not sure how to port the design to Stratix for Gen3x4 or Gen3x8 ... I am currently telling QSYS that the TXS port width is 20 bits and running the Generate to get the Verilog RTL. I then altering the TXS width parameter to 64 bits and concatenating the upper 44 bits to the address into the TXS slave as a hard wired NIOS address -> 64 bit PCIe address translation.

Any other ideas on how to port the original design ?