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For your information, there is one set of DIP switch (SW6) on Stratix V dev kit related to PCIe and that is to select the lane width.
Ensure you have set the DIP switches to factory default settings.
Refer to Figure 4-2 of 'Stratix V GX FPGA Development Kit User Guide' at
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_svgx_fpga_dev_kit.pdf --- Quote End ---
Well, a design (encrypted) was successfully programmed in the FPGA on the board and it worked... instead I was indeed referring to an example design (PCIe AVMM DMA) I was not able to send to the same path... so I would not mess with the switches on the board...
Anyway, I'll try the DDR3 example as soon as I can... the only gotcha is that everything is Quartus II 14.0v and it does not migrate easily/automatically to 15v, so you gotta stick to 14.0v or manually tweak the Qsys project...
Thank you SKBEH for what you give here.
Honored Contributor
