Stratix V PCIe HIP not supporting Avalon MM Gen3 x8 I/F

So I moved to the gen3x4 design and added NIOS II and some On Chip Memory ... the card works fine so far except for the gen3_led doesn't com on ... when in a gen3 slot the configuration link status indicates a 0x43 which is gen3x4 ... but no gen3_led only the L0_led and the four link leds are on indicating x4 and alive_led flashing ... tomorrow I will confirm gen3x4 operation by adding an analyzer. Almost identical designs that are gen3x8 have the same top_hw.v design where all the LED's are decoded .. the gen3_led is decoded off

assign gen3_speed = tl_cfg_tl_cfg_sts[32:31] == 2'b11;

I would like to find the documentation on tl_cfg_tl_cfg_sts but other elements of it like the link width appear to work.

With the simulation Generation flipping out on me .... (see the other thread) I am stuck.

This vector is generated by altpcie_sv_hip_ast_hip_status_bridge ... that I can't find anything on either. I guess I will try the PCIe ug from Altera.

Thanks, Bob.