New ContributorHi Team,
Some of the initial data on the data_io port of the PHYlite is missing when it reaches the data_to_core port. Additionally, although one group is a copy of another, I am observing data deviations on the data_to_core port. Can anyone help me debug this issue?
Group 0:
8byte of missing data in group 0
Group 2
Configuration setting
Regular ContributorHi,
Can you check the design for the timing compilation?
Maybe there is timing issue in the design.
Can you test with the example design as well?
Regards,
Adzim
New ContributorI am facing this issue during functional simulation
New ContributorHi AdzimZM,
I evaluated the example simulation design using my PHY Lite IP configuration settings. Even within the example design, I observed frequent occurrences of incorrect read data, as illustrated below.
The data sampling mechanism from data_io to data_to_core is not entirely clear to me(the alignment of data on data_to_core(LSB to MSB) differs between the example design and PHY Lite document). In my actual design, the data_to_core signal fails to capture the initial few data words. In contrast, the example design does capture the initial data, but intermittently misses some intermediate data.
Kindly assist me in identifying and resolving the issue
Group 1,
Group 0,
correct
Mismatch
Regular ContributorHi,
I tried to replicate the issue at my end, but the result is passing, and simulation is successful.
Can you confirm the version of PHYLite IP, Quartus and simulator?
Regards,
Adzim
New ContributorHi Admiz,
Phylite_IP version - 19.3.0
Quartus Version -Quartus Prime Design Software
Version 22.1.0 Build 174 03/30/2022 SC Pro Edition
Simulator - Questa Intel FPGA Edition-64 vsim 2023.4 Simulator 2023.10 Oct 9 2023
Regular ContributorHi
I think since the dynamic reconfiguration is enabled, there are calibration and testing will be done to the IP.
This process will expect some mismatch of the data and it will run for multiple loops.
Regards,
Adzim
New Contributorokay .In my design , I am facing issue of sampling initial few bytes of data .How do I resolve this issue?
New ContributorHi AdzimZM,
In dynamic reconfiguration , though I increase the tap value around mid(262) for pin input , I didn't find any delay in actual simulation .I referred the below one. Here I have doubt that how will we select the dq pin between 2 and 9.Additionally at specific pin selection (from 2 to 9) , what I need to keep at field[8:7]?
Please help me with this
New ContributorHi,
Is there any update?
