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NMR's avatar
NMR
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1 year ago

Stratix 10 PHYlite : initial data on the data_io port of the PHYlite is missing at data_to_core

Hi Team, Some of the initial data on the data_io port of the PHYlite is missing when it reaches the data_to_core port. Additionally, although one group is a copy of another, I am observing data devi...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
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1 year ago

Hi


I think since the dynamic reconfiguration is enabled, there are calibration and testing will be done to the IP.

This process will expect some mismatch of the data and it will run for multiple loops.


Regards,

Adzim


  • NMR's avatar
    NMR
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    1 year ago

    okay .In my design , I am facing issue of sampling initial few bytes of data .How do I resolve this issue?

  • NMR's avatar
    NMR
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    1 year ago

    Hi AdzimZM,

    In dynamic reconfiguration , though I increase the tap value around mid(262) for pin input , I didn't find any delay in actual simulation .I referred the below one. Here I have doubt that how will we select the dq pin between 2 and 9.Additionally at specific pin selection (from 2 to 9) , what I need to keep at field[8:7]?

    Please help me with this

    • NMR's avatar
      NMR
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      1 year ago

      Hi,

      Is there any update?