Stratix 10 PHYlite : initial data on the data_io port of the PHYlite is missing at data_to_core

Hi AdzimZM,

I evaluated the example simulation design using my PHY Lite IP configuration settings. Even within the example design, I observed frequent occurrences of incorrect read data, as illustrated below.

The data sampling mechanism from data_io to data_to_core is not entirely clear to me(the alignment of data on data_to_core(LSB to MSB) differs between the example design and PHY Lite document). In my actual design, the data_to_core signal fails to capture the initial few data words. In contrast, the example design does capture the initial data, but intermittently misses some intermediate data.

Kindly assist me in identifying and resolving the issue

Group 1,

Group 0,

correct

Mismatch