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dsun01's avatar
dsun01
Icon for Contributor rankContributor
3 years ago
Solved

run AN708 on Quartus 21.3

Dear Support,

I downloaded AN708_q170. try to run it in my quartus 21.3. after I update the IP.

the platform designer, told me

Error: top.DUT.dma_rd_master: DUT.rd_dts_slave (0x80000000..0x80001fff) overlaps emif_0.ctrl_amm_0 (0x0..0xffffffff)
Error: top.mm_clock_crossing_bridge_0.m0: emif_0.ctrl_amm_0 (0x0..0xffffffff) is outside the master's address range (0x0..0xfffffff)
Error: qsys-generate failed with exit code 3: 2 Errors, 5 Warnings
Error: top.DUT.dma_rd_master: DUT.rd_dts_slave (0x80000000..0x80001fff) overlaps emif_0.ctrl_amm_0 (0x0..0xffffffff)
Error: top.mm_clock_crossing_bridge_0.m0: emif_0.ctrl_amm_0 (0x0..0xffffffff) is outside the master's address range (0x0..0xfffffff)
Error: qsys-generate failed with exit code 3: 2 Errors, 5 Warnings

is there an PCIe with external memory example in 21.3 format. don't tell me that I have to install a quartus version 17.

Thanks,

David

  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi David,

    I did some investigation and determined that Quartus 17.0 onwards don't allow test bench generation with critical hard blocks not connected. The reference design attached in AN708 was generated using Quartus 17.0 only. This Quartus version allows test bench generation with hip_pipe and hip_control conduit exported. My suggestion at the moment will be please revert back to Quartus 17.0 to use QYS feature to generate the test bench system.

    To encounter this, I have opened an internal case to resolve this; so the AN708 simulation and test bench generation are also validated to allow migration. Hope the related team will work on this.
    Please accept my apologies for the frustration you have faced. Hope this is clarified.

    Regards,

    Wincent_Intel

30 Replies

  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    3 years ago

    Dear Intel friends,

    after some struggle, I can compile the projects. I have the following errors while I generate simulation example. could anyone give me some suggestion to solve the problem.

    Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\top.qsys (Access is denied)
    Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\sriov_mcdma_app_g3x8_256b.qsys (Access is denied)
    Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\rddc_mc_256b.qsys (Access is denied)
    Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\wrdc_mc_256b.qsys (Access is denied)
    Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
    Error: Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\top.qsys (Access is denied)
    Error: There were errors creating the testbench system.

    I attached the Quartus 21.3 compiled project, it can be compiled but not know anything else.

    Thank you,

    David

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi,

      Can you share with me how your resolved the compilation issue?

      For error "Error: Unexpected error writing the ensemble: java.io.FileNotFoundException:"

      Can you please check if The software was installed under Program Files folder ?
      If YES, I would suggest you to try unistalled Quartus Suite and installed again on root directory (C:\Altera).

      Probably the problem was the space in the installation path ("Program Files").

      Hope this help,

      Regards,

      Wincent_Intel

      • dsun01's avatar
        dsun01
        Icon for Contributor rankContributor
        3 years ago

        Hi Wincent_Intel

        the Quartus was installed at C:\intelFPGA_pro\21.3

        for the compilation,

        1. did an IP auto update.

        2. the new IP not support 12 bit CAS( or RAS I can't remember), first time I change it to 16 bits, then the error happens. after I change it to 14 bits. then it compile OK.

        Thank you,

        David

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago


    Hi,


    Thank you for reaching out.

    Just to let you know that Intel has received your support request and I am assigned to work on it.

    Allow me some time to look into your issue. I shall come back to you with findings.


    Thank you for your patience.


    Best regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Thanks for sharing with me.

    for the Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: issue

    Normally You will receive the above mentioned error in the SOPC Builder if you have logged into a PC without admin priveleges

    and you try and generate one of the example designs that is located in the default installation.

    You can workaround this error by copying the example design from the installation directory into a new directory elsewhere on the PC.


    Can you please try it ?

    Regards

    Wincent_Intel



    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      I copied the project into a different directory, the software generates same error message.

      by the way, I can run other very complex simulation with Jesd204b and DDR4 with Nios2 core without any problem.

      I am learning PCIe now, don't know why I have this problem.

      Thank you for helping.

      David

      • dsun01's avatar
        dsun01
        Icon for Contributor rankContributor
        3 years ago

        good news, after I change the owner of the directory, the original error disappeared.

        bad news was that new errors appeared.

        Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
        Error: Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
        Error: There were errors creating the testbench system.

    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      by the way, could you duplicate the problem on your platform, if not, that means related to the tool installation. otherwise, is the project/software itself problem

      thanks,

      David

    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      I set the testbench output directory to

      C:/FPGA/aPcie/AN708_q170_projectCopy/top_tb/

      why the tools want to update the files in the

      C:\intelFPGA_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design?

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        3 years ago

        Hi Dsun,

        Glad that the issue solve, are you using company workstation/computer ?
        Suspect some file access routes might be encrypted...

        For the new issue can you please remove all the unnecessary custom IP paths mentioned in IP Search Path and try to generate testbench again ?