Forum Discussion
run AN708 on Quartus 21.3
- 3 years ago
Hi David,
I did some investigation and determined that Quartus 17.0 onwards don't allow test bench generation with critical hard blocks not connected. The reference design attached in AN708 was generated using Quartus 17.0 only. This Quartus version allows test bench generation with hip_pipe and hip_control conduit exported. My suggestion at the moment will be please revert back to Quartus 17.0 to use QYS feature to generate the test bench system.
To encounter this, I have opened an internal case to resolve this; so the AN708 simulation and test bench generation are also validated to allow migration. Hope the related team will work on this.
Please accept my apologies for the frustration you have faced. Hope this is clarified.Regards,
Wincent_Intel
Hi Wchiah
We are on the same page now. the project I uploaded can be compiled in Quartus 21.3.
My question/problem was
after open the top.sys at the platform designer.
when generate testbench system.
Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
Error: Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
Error: There were errors creating the testbench system.
as a new user to PCIe and DDR system, I think the simulation environment will be very helpful to make deep understand of the interface.
if the platform designer doesn't support to create the simulation environment automatically.
is it possible to create a simulation for this PCIe and DDR example?
How?
Thank you very much
David
Hi David,
I did some investigation and determined that Quartus 17.0 onwards don't allow test bench generation with critical hard blocks not connected. The reference design attached in AN708 was generated using Quartus 17.0 only. This Quartus version allows test bench generation with hip_pipe and hip_control conduit exported. My suggestion at the moment will be please revert back to Quartus 17.0 to use QYS feature to generate the test bench system.
To encounter this, I have opened an internal case to resolve this; so the AN708 simulation and test bench generation are also validated to allow migration. Hope the related team will work on this.
Please accept my apologies for the frustration you have faced. Hope this is clarified.
Regards,
Wincent_Intel
- dsun013 years ago
Contributor
Hi Wchiah,
Thank you very much for the investigation and a clear conclusion. it is very hard to get an ideal solution, but it is very critical to know what is going to happen, especially for a learner. I am not sure I would like to go to Quartus 17. I will spend more time to read ug_a10_pcie_avmm_dma-683425-666332. by the way, beside rely on AN708, is there other example with PCIe and DMA and DDR? the goal is to use PCIe in my application not AN708 itself.
appreciate you time and patience.
David
- Wincent_Altera3 years ago
Regular Contributor
Hi David,
Is okay, I am happy if can help you. I believe you can be an expert somewhere in the future.
Meanwhile, we can learn together at the moment, I also learn quite a lot from the question you ask right now.
Thanks for actively reply and provide the needed information as well for us to further debug this.
For example related to Arria 10 either PCIe or DMA, you may refer to Intel FPGA design store.
Hope this answer your question,
Regards,
Wincent_Intel
- dsun013 years ago
Contributor
Wchiah,
If I view this from a different angle, the last update of the PCIe is version 17. which means that Intel gave up the support of the PCIe. I have heard many times that I should use 3rd party PCIe IP. I insisted to trust Intel to its IP. I am kind of understand what my friend's advice now. once it is possible, I should check a 3rd party IP.
Thank you
David
- Wincent_Altera3 years ago
Regular Contributor
Hi David,
I understand your frustration, but I would emphasize the support until version 17.0 is only specific Arria 10 AN708 design example.
For PCIe IP, the latest version of Quartus do fully support all the way AVST, AVMM to PCIe DMA, and other PCIe design as well.
Besides that, in the latest Agilex device, it support PCIe gen5 as well as some other useful design.
The best I can help at the moment is help to submit an internal ticket to mention that there is a user who request an updated version for Arria 10 AN708 design example that supports latest Quartus version.
Hope this help, let me know if anything else that you feel I can help more.
Regards,
Wincent_Intel
- dsun013 years ago
Contributor
Wchiah,
Here is a little background of my project, I have an evaluation package from TI data acquisition chip AFE58JD48. the original system is 16 ADCs ( 8 lane of JESD204B, upstream is USB3). I need to use 64 ADCs ( 16 lane of JESD204B), USB3 is not fast enough, so I need to replace the USB3 module to PCIe3. the original design has interface from USB3 to DDR4 control, and I2C. if I have an example like AN708, I can learn how the PCIe interfaced with DDR. that will make it easier for me to integrate the PCIe interface into the system.
besides AN708, any suggestion can make me go forward faster than start from the PCIe user guide will be appreciated.
Thank you for help.
David
- Wincent_Altera3 years ago
Regular Contributor
Hi David,
If you have Stratix 10 , you can try to look at
- https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/pcie-support.html
- Gen3x8 Avalon -MM DMA with External DDR3/DDR4 Memory (AN 829)
Other than that, you may check on
- Intel® FPGA Technical Training Catalog, It help me when I was a pioneer in FPGA area.
- https://www.intel.com/content/www/us/en/support/programmable/support-resources/fpga-training/catalog.html?s=Relevancy
- Also there is an Official Intel FPGA youtube channel which explain step to step function
- https://www.youtube.com/c/IntelFPGA
For PCIe and DDR, you may refe to IP support center
- PCIE , https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/pcie-support.html
- EMIF , https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/emif-support.html
Regards,
Wincent_Intel
- dsun013 years ago
Contributor
Hi Wchiah
In fact, AN829 is what I am looking for, but the title didn't mention the DDR interface, so I didn't check in content.
I think this time I do find somewhere to start with.
Appreciate your help. have a good weekend
David
- dsun013 years ago
Contributor
Wchiah,
While I ran simulation of the AN829, I got this error message.
# ** Error (suppressible): (vopt-14408) Intel Starter FPGA Edition recommended capacity is 5000 non-OEM instances. There are 9597 non OEM instances. Expect performance to be severely impacted.
I guess this is because the free simulation tools provide by Intel does not support this complicate project, is that right?
how to solve this problem if not pay the professional simulation tools?
Thank you,
David
- dsun013 years ago
Contributor
Hi Wchiah
I start a new struggle journey on AN829 and posted a challenge at a new thread.
AN829 simulation ran but failed - Intel Communities
hope you can have a look and give me some suggestion.
this needs more detailed investigation into the example because I guess the problem is not just on the tool revision level.
we can close this thread and thank you for all your help.
David
- Wincent_Altera3 years ago
Regular Contributor
Hi David,
This error is issued when the design capacity for the simulator is exceeded.
See page-11 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20352.pdf
'Known Differences Between the Questa-Intel FPGA Edition and ModelSim* - Intel FPGA Edition'
Few suggestions:
1) In Quartus -> Message tab, right click 'Message', select 'Suppress -> Suppress Message / Suppress Messages with Matching ID to suppress the message。
2) I found this KDB, it uses the "suppress" option along with vsim command ( vsim -suppress 10000)
In your case, probably can try 'vsim -suppress 14408' instead of 'suppress = 14408'
https://www.intel.com/content/www/us/en/support/programmable/articles/000074348.htmlHope this help.
Regards,
Wincent_Intel
- Wincent_Altera3 years ago
Regular Contributor
Hi David,
Thanks, With that said I am closing this thread.
If you feel your support experience was less than a 9 or 10,
please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.
Great to work with you in this issue
Regards,
Wincent_Intel