Forum Discussion
Contributorrun AN708 on Quartus 21.3
Hi David,
I did some investigation and determined that Quartus 17.0 onwards don't allow test bench generation with critical hard blocks not connected. The reference design attached in AN708 was generated using Quartus 17.0 only. This Quartus version allows test bench generation with hip_pipe and hip_control conduit exported. My suggestion at the moment will be please revert back to Quartus 17.0 to use QYS feature to generate the test bench system.
To encounter this, I have opened an internal case to resolve this; so the AN708 simulation and test bench generation are also validated to allow migration. Hope the related team will work on this.
Please accept my apologies for the frustration you have faced. Hope this is clarified.Regards,
Wincent_Intel
ContributorDear Intel friends,
after some struggle, I can compile the projects. I have the following errors while I generate simulation example. could anyone give me some suggestion to solve the problem.
Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\top.qsys (Access is denied)
Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\sriov_mcdma_app_g3x8_256b.qsys (Access is denied)
Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\rddc_mc_256b.qsys (Access is denied)
Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\wrdc_mc_256b.qsys (Access is denied)
Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
Error: Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\top.qsys (Access is denied)
Error: There were errors creating the testbench system.
I attached the Quartus 21.3 compiled project, it can be compiled but not know anything else.
Thank you,
David
Regular ContributorHi,
Can you share with me how your resolved the compilation issue?
For error "Error: Unexpected error writing the ensemble: java.io.FileNotFoundException:"
Can you please check if The software was installed under Program Files folder ?
If YES, I would suggest you to try unistalled Quartus Suite and installed again on root directory (C:\Altera).
Probably the problem was the space in the installation path ("Program Files").
Hope this help,
Regards,
Wincent_Intel
- dsun01
Hi Wincent_Intel
the Quartus was installed at C:\intelFPGA_pro\21.3
for the compilation,
1. did an IP auto update.
2. the new IP not support 12 bit CAS( or RAS I can't remember), first time I change it to 16 bits, then the error happens. after I change it to 14 bits. then it compile OK.
Thank you,
David
- Wincent_Altera
Hi David,
Can I know where you change the CAS/RAS bits ? is it inside platform designer ?Hoping to hear back from you.
Regards,
Wincent_Intel- dsun01
Yes, use platform designer. original package set to 12bit. the first time I choose 16 bits. there is a conflict of the base address. after I change it to 14 bits, it compiled.
thank you,
