Forum Discussion
Contributorrun AN708 on Quartus 21.3
Hi David,
I did some investigation and determined that Quartus 17.0 onwards don't allow test bench generation with critical hard blocks not connected. The reference design attached in AN708 was generated using Quartus 17.0 only. This Quartus version allows test bench generation with hip_pipe and hip_control conduit exported. My suggestion at the moment will be please revert back to Quartus 17.0 to use QYS feature to generate the test bench system.
To encounter this, I have opened an internal case to resolve this; so the AN708 simulation and test bench generation are also validated to allow migration. Hope the related team will work on this.
Please accept my apologies for the frustration you have faced. Hope this is clarified.Regards,
Wincent_Intel
ContributorI set the testbench output directory to
C:/FPGA/aPcie/AN708_q170_projectCopy/top_tb/
why the tools want to update the files in the
C:\intelFPGA_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design?
Regular ContributorHi Dsun,
Glad that the issue solve, are you using company workstation/computer ?
Suspect some file access routes might be encrypted...
For the new issue can you please remove all the unnecessary custom IP paths mentioned in IP Search Path and try to generate testbench again ?
- dsun01
Hi Wchiah,
How to find the IP search path? how do I know which is unnecessary?
by the way, can Intel provide a version of AN708 that can run with Quartus 21.3. I am learning generic PCIe IP by Intel example. I am not an Intel Platform expert. can I assume that there are not many people use Intel PCIe ip on latest quartus software.
if it is not straight forward to me, hard to believe it is an easy job for other engineers.
I really appreciate your help to solve this problem, should it be Intel's responsibility to provide a working example on the latest platform?
is the latest release based on Quartus 17?
Thank you,
David
- Wincent_Altera
Hi David,
I understand your feeling. That is why I am here to help you.
I try the .qar file provided by you without modifying anything (just simple run full compilation)
Using Quartus Pro Edition 21.3 . The design is able to compile without any error at all.Can you please try it again ? or on another laptop perhaps?
Regards,
Wincent_Intel
- dsun01
Hi Wchiah
We are on the same page now. the project I uploaded can be compiled in Quartus 21.3.
My question/problem was
after open the top.sys at the platform designer.
when generate testbench system.
Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
Error: Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
Error: There were errors creating the testbench system.as a new user to PCIe and DDR system, I think the simulation environment will be very helpful to make deep understand of the interface.
if the platform designer doesn't support to create the simulation environment automatically.
is it possible to create a simulation for this PCIe and DDR example?
How?
Thank you very much
David
- dsun01
Hi Wchiah,
This is my personal computer; I am the only user. I am using win10. it is very hard to understand why I don't have the right to access some file because I am the administrator. the more intelligent of the Windows software, the harder to understand how to use it, same as Quartus.
appreciate your help.
David
