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dsun01's avatar
dsun01
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3 years ago
Solved

run AN708 on Quartus 21.3

Dear Support, I downloaded AN708_q170. try to run it in my quartus 21.3. after I update the IP. the platform designer, told me Error: top.DUT.dma_rd_master: DUT.rd_dts_slave (0x80000000..0...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi David,

    I did some investigation and determined that Quartus 17.0 onwards don't allow test bench generation with critical hard blocks not connected. The reference design attached in AN708 was generated using Quartus 17.0 only. This Quartus version allows test bench generation with hip_pipe and hip_control conduit exported. My suggestion at the moment will be please revert back to Quartus 17.0 to use QYS feature to generate the test bench system.

    To encounter this, I have opened an internal case to resolve this; so the AN708 simulation and test bench generation are also validated to allow migration. Hope the related team will work on this.
    Please accept my apologies for the frustration you have faced. Hope this is clarified.

    Regards,

    Wincent_Intel

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thanks for sharing with me.

for the Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: issue

Normally You will receive the above mentioned error in the SOPC Builder if you have logged into a PC without admin priveleges

and you try and generate one of the example designs that is located in the default installation.

You can workaround this error by copying the example design from the installation directory into a new directory elsewhere on the PC.


Can you please try it ?

Regards

Wincent_Intel



  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    3 years ago

    I copied the project into a different directory, the software generates same error message.

    by the way, I can run other very complex simulation with Jesd204b and DDR4 with Nios2 core without any problem.

    I am learning PCIe now, don't know why I have this problem.

    Thank you for helping.

    David

    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      good news, after I change the owner of the directory, the original error disappeared.

      bad news was that new errors appeared.

      Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
      Error: Error: can't read "intf_use_partner(pcie_rstn)": no such element in array
      Error: There were errors creating the testbench system.

  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    3 years ago

    by the way, could you duplicate the problem on your platform, if not, that means related to the tool installation. otherwise, is the project/software itself problem

    thanks,

    David

  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    3 years ago

    I set the testbench output directory to

    C:/FPGA/aPcie/AN708_q170_projectCopy/top_tb/

    why the tools want to update the files in the

    C:\intelFPGA_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design?

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi Dsun,

      Glad that the issue solve, are you using company workstation/computer ?
      Suspect some file access routes might be encrypted...

      For the new issue can you please remove all the unnecessary custom IP paths mentioned in IP Search Path and try to generate testbench again ?

      • dsun01's avatar
        dsun01
        Icon for Contributor rankContributor
        3 years ago

        Hi Wchiah,

        How to find the IP search path? how do I know which is unnecessary?

        by the way, can Intel provide a version of AN708 that can run with Quartus 21.3. I am learning generic PCIe IP by Intel example. I am not an Intel Platform expert. can I assume that there are not many people use Intel PCIe ip on latest quartus software.

        if it is not straight forward to me, hard to believe it is an easy job for other engineers.

        I really appreciate your help to solve this problem, should it be Intel's responsibility to provide a working example on the latest platform?

        is the latest release based on Quartus 17?

        Thank you,

        David