rdusedw not count in my dcfifo

Question

rdusedw not count in my dcfifo  EP3C16F256C8N Quartus II 9.1 sp2 a dcfifo generated by megawizard plugin manager. rdclk: 75MHz wrclk: 40MHz this is a snipping image of a running signaltap(rdclk as the sample clock): http://www.alteraforum.com/forum/attachment.php?attachmentid=3531&amp;stc=1&amp;d=1295551799  the rdusedw is always 0. this is the code from the generated .v file 		dcfifo_component.intended_device_family = "Cyclone III",
		dcfifo_component.lpm_numwords = 256,
		dcfifo_component.lpm_showahead = "OFF",
		dcfifo_component.lpm_type = "dcfifo",
		dcfifo_component.lpm_width = 32,
		dcfifo_component.lpm_widthu = 8,
		dcfifo_component.overflow_checking = "ON",
		dcfifo_component.rdsync_delaypipe = 5,
		dcfifo_component.underflow_checking = "ON",
		dcfifo_component.use_eab = "ON",
		dcfifo_component.write_aclr_synch = "ON",
		dcfifo_component.wrsync_delaypipe = 5;  why rdusedw not count after wrreq assert?

altera_forum · Answer

possibility 1: is rdclk connected to fifo?

possibility 2: you have plenty of delay. Have you looked further down in signaltap?

possibility 3: you have written till fifo was full and stayed full with rdcounter rolled over to zero and stayed at zero.

altera_forum · Answer

--- Quote Start ---

possibility 1: is rdclk connected to fifo?

possibility 2: you have plenty of delay. Have you looked further down in signaltap?

possibility 3: you have written till fifo was full and stayed full with rdcounter rolled over to zero and stayed at zero.

--- Quote End ---

possibility 1: I use "...|fifo0:fifo0_inst|rdclk" as the sampling clock of signaltap, if no rdclk, no data in signaltap.

possibility 2: I get 256 samples each trigger, the rdusedw never changes.

possibility 3: There is a "assign avl_irq = (rdusedw >= 8'd128);" in my design, when I use avl_irq = 1 as the trigger condition, no data captured. And it never stops writting data to fifo.

altera_forum · Answer

Don't lose hope, it must something out there. Fifo usually work.

presence of sampling clock does not mean fifo read clock is wired to fifo, simple to rule out.

Your trigger may not work if it misses the startup stage when fpga is configured and write clock starts outright then it will fill up your fifo and the count will settle at zero unless you read fast enough.

Just thoughts...

altera_forum · Answer

I also note that your write clock is less than half speed of read clock as meausred visually in signaltap waveforms. This may give some clue about accurcy of your clocking

altera_forum · Answer

Hard to tell why with the signals that are sampled.  I would sample the clear signal to make sure you are not accidentally holding the FIFO in reset as well as sample the empty and full bits for good measure.  Like kaz said, your FIFO might be full and as a result the empty bits rolled over to be 0.

Forum Discussion

rdusedw not count in my dcfifo

8 Replies

Recent Discussions

Request for private case.

MAX10 TSE reference design

Confusion for TX Clock direction for Triple Speed 1G Ethernet IP?

Does AXI Multi-Channel DMA IP support CvP ?

Regarding the TX settings of MIPI CSI2 IP