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possibility 1: is rdclk connected to fifo?
possibility 2: you have plenty of delay. Have you looked further down in signaltap?
possibility 3: you have written till fifo was full and stayed full with rdcounter rolled over to zero and stayed at zero.
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possibility 1: I use "...|fifo0:fifo0_inst|rdclk" as the sampling clock of signaltap, if no rdclk, no data in signaltap.
possibility 2: I get 256 samples each trigger, the rdusedw never changes.
possibility 3: There is a "assign avl_irq = (rdusedw >= 8'd128);" in my design, when I use avl_irq = 1 as the trigger condition, no data captured. And it never stops writting data to fifo.
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