rdusedw not count in my dcfifo

Don't lose hope, it must something out there. Fifo usually work.

presence of sampling clock does not mean fifo read clock is wired to fifo, simple to rule out.

Your trigger may not work if it misses the startup stage when fpga is configured and write clock starts outright then it will fill up your fifo and the count will settle at zero unless you read fast enough.

Just thoughts...