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Honored Contributor
Honored Contributorrdusedw not count in my dcfifo
rdusedw not count in my dcfifo EP3C16F256C8N Quartus II 9.1 sp2 a dcfifo generated by megawizard plugin manager. rdclk: 75MHz wrclk: 40MHz this is a snipping image of a running signal...
Altera_ForumHonored Contributor
Honored ContributorHard to tell why with the signals that are sampled. I would sample the clear signal to make sure you are not accidentally holding the FIFO in reset as well as sample the empty and full bits for good measure. Like kaz said, your FIFO might be full and as a result the empty bits rolled over to be 0.
