rdusedw not count in my dcfifo

Thanks kaz!

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the count will settle at zero unless you read fast enough

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Will the rdusedw settle at 0 after fifo is full? you mean it will not count cycling when rolles over, from 255 to 0, then to 1, 2, ... I really don't know about this.

The read end of the fifo is connected to a nios cpu via avalon memmap slave, and read in a ISR, may be I should apply a clear signal just after the ISR being registered.

But... settle at 0... if it will settle at some value, or in another word, saturate at some value, why it's not 255 but 0? settle at 0, result in dead locking of the fifo, but settle at 255, only losing of data. Anyway, I will try appling a clear at read end...

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I also note that your write clock is less than half speed of read clock as meausred visually in signaltap waveforms.

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I don't think so, 2 low level samples are gona happen:

http://www.alteraforum.com/forum/attachment.php?attachmentid=3533&stc=1&d=1295583980

frequency -> edges count

duty -> possibility of high level

sample a 50% duty cycled clock by another clock, always get equal numbers of high levels and low levels, unless their freqs share large common divisor.