Outputs from decimatingCIC are shifted (i.e. input at channel c2 appears at c0)

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Hi everyone,

From these setting I need to feed input vector of 7 because each input has TDM of 5 (100MHz/20MHz).

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can you explain the above, I don't get it.

are the 32 channels serial or parallel?

Hello kaz,

Thank you very much for your reply. I attached the filter report in this comment.

If I under stand it correctly I need to put 32 channels in both serial and parallel.

like this:

Input Data Format (Repeats every 5 clock cycles)

<c00><c01><c02><c03><c04>

<c05><c06><c07><c08><c09>

<c10><c11><c12><c13><c14>

<c15><c16><c17><c18><c19>

<c20><c21><c22><c23><c24>

<c25><c26><c27><c28><c29>

<c30><c31><c32><c33><c34>

I put every 5 data in series and there are 7 of these serialized signals I fed to the CIC filter.

I expect the output signals to be like what it is specified in the report:

Output Data Format (Repeats every 160 clock cycles)

<c00><c01><c02><c03><c04><c05>.......<c30><c31><---><---><---><--->.....

However, What I got is something like..

<c01><c02><c03><c04><c00><c05>.......<cxx><cxx><---><---><---><--->.....

The order of the data seems to be shifted.

Thank you.

Thank you again Kaz,

I have connected the data, valid, and channel right infront of the Filter to ChanView.

The output signals from channel view was as expected, no shift at the input. All data are displayed at the proper channels.

However, I tried to delay only the data line by 1 sample delay. As a result, CICfilter outputs are now in the right order.

I think this is might be only a temorary solution because once I do this the data and channel number are not aligned at the input of CICfilter any more.

Could it be that there is a missing sample delay in the DecimatingCIC filter because I have to compensate it in front of the block?

Thank you very much.

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Thank you again Kaz,

I have connected the data, valid, and channel right infront of the Filter to ChanView.

The output signals from channel view was as expected, no shift at the input. All data are displayed at the proper channels.

However, I tried to delay only the data line by 1 sample delay. As a result, CICfilter outputs are now in the right order.

I think this is might be only a temorary solution because once I do this the data and channel number are not aligned at the input of CICfilter any more.

Could it be that there is a missing sample delay in the DecimatingCIC filter because I have to compensate it in front of the block?

Thank you very much.

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My own experience with DSPBuilder is that channel input is(or was) actually ignored (not driving anything internally) and instead the design counts from first valid. It might be related to that so double check the start of valid input

Hello Kraz,

Thank you very much. The problem is solved!

I double checked the first valid. At the first valid the channel and data are from c1 instead of c0. This is because the counter setup, which I use to generate channel number and select data, was set to [<_initial_value> <_modulo> <_step_size>]= [0 5 1], and the output became 1 at the first valid.

Instead I have to set it to [-1 5 1] to get the first channel number to 0 at the first valid. Once I did this everything looks nice!

Thanks a lot.

Tormour