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Thank you again Kaz,
I have connected the data, valid, and channel right infront of the Filter to ChanView.
The output signals from channel view was as expected, no shift at the input. All data are displayed at the proper channels.
However, I tried to delay only the data line by 1 sample delay. As a result, CICfilter outputs are now in the right order.
I think this is might be only a temorary solution because once I do this the data and channel number are not aligned at the input of CICfilter any more.
Could it be that there is a missing sample delay in the DecimatingCIC filter because I have to compensate it in front of the block?
Thank you very much.
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My own experience with DSPBuilder is that channel input is(or was) actually ignored (not driving anything internally) and instead the design counts from first valid. It might be related to that so double check the start of valid input
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