not able to generate sdo for arria 10 soc for post-synthesis timing simulation

Question

There is a standard procedure mentioned in so many places/links to do timing simualtion for any project using modelsim from quartus which is called as gate-level simulation also.

I followed that and sucessfully able to generate EDA Netlist which is useful for timing simulation and it will generate after fitter which is the correct flow.

I am doing simulation for arria 10 soc device 10AS066N3F40E2SG

```Info: ***********************

Info: Running Quartus Prime EDA Netlist Writer

Info: Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition

Info: Processing started: Wed Jan 15 11:14:14 2020

Info: Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition

Info: Processing started: Wed Jan 15 11:14:14 2020

Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off ghrd_10as066n2 -c ghrd_10as066n2

Warning (20013): Ignored 16 assignments for entity "FIFODepth8Width36" -- entity does not exist in design

Warning (20013): Ignored 34 assignments for entity "FIFODepth8Width36_fifo_161_baxh53i" -- entity does not exist in design

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.

Info (204019): Generated file ghrd_10as066n2.vho in folder "C:/Users/venkatesh/Codes/enhanced_rbk2_1/CFARDesign/a10_soc_devkit_ghrd/simulation/modelsim/" for EDA simulation tool

Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 4 warnings

Info: Peak virtual memory: 5218 megabytes

Info: Processing ended: Wed Jan 15 11:14:37 2020

Info: Elapsed time: 00:00:23

Info: Total CPU time (on all processors): 00:00:22

Info: Peak virtual memory: 5218 megabytes

Info: Processing ended: Wed Jan 15 11:14:37 2020

Info: Elapsed time: 00:00:23

Info: Total CPU time (on all processors): 00:00:22```

Hey just see warning 10905 where as it's saying .vho is only supported and .sdo is not supported and that is the one required to do timing simulation. what is this i am getting why not generating for arria 10 soc device where as in online and all it's specified .sdo generation not supported for CYCLONE V , ARRIA V and MAX and other some lower devices. but not mentioned for arria 10 but in tool it's saying like that. without that how timing simulation can be done..?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-tp-simulation.pdf#page=5

How you will help me now..? I really want to do timing simulation as I want to run my design for higher clocks in fpga. for that I can't check every register in hardware without simulation to make it work correctly.

venkateshsathar · Answer

Yeah I can see Arria 10 is not there in support list. is there any way to see timining simulation then still...? because in hardware i see really weird outputs. In TimeQuestAnalyser It didn't have any problems with the nets that I am seeing real time where the problem is there. It will be really tough to solve by seeing everything after testing in hardware. can you suggest any simple approaches to solve this problems of timing..? First thing is I am following design standards already for higher clock as mentioned in the following training.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/simulation/modelsim/exm-timing-verilog-msaltera.html

apart from this can you help me in any other way?

kennyt_altera · Answer

Hi,Timing simulation should be avoided for arria 10 device. you can refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii5v3.pdf page 1-2.What you can do is the following:1) make sure you written the correct constrain in the sdc.2) timing is close in the timing analyzer3) signal tap on those failure pathThanks,

venkateshsathar · Answer

Point 1 and 2 i am already doing.

Regarding point 3 I already told that all the paths i Can't monitor in my design in signal tap as there as so many. Main thing is that The paths which are failing in real time are not even shown as failed in timing analyzer.

kennyt_altera · Answer

Can provide more specific failure symptom? Without know what are the failure on your hardware, would be hard to provide advice.

Does your gate level simulation show the expected value? Even though the gate level simulation does not use .sdo but it still use the fitter netlist to do the simulation.

venkateshsathar · Answer

yeah it is showing the expected values only after using .vho files for vhdl gate level simulation. For example , the problem is like i have an array where based on the input data and index it get accumulated and stored in an data array. Now the input data is fine and index is fine. but the data output read from array is not as expected in hardware when seeing in signal tap. This time best thing is to monitor that array also so that each time accumulating properly or not we will know. but that array is too big that we can do signal tap on that.  still i just monitored some index of the array and those are fine. I want to monitor all then only we can know where the problem is happening and then we can correct. this kind of things in timining simulation when monitoring all signals very easy but in hardware somewhat tough like I told the case.

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not able to generate sdo for arria 10 soc for post-synthesis timing simulation

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