Forum Discussion
VenkateshSathar
Occasional Contributor
Occasional Contributornot able to generate sdo for arria 10 soc for post-synthesis timing simulation
There is a standard procedure mentioned in so many places/links to do timing simualtion for any project using modelsim from quartus which is called as gate-level simulation also. I followed that and...
KennyT_altera
Super Contributor
Super ContributorHi,
Timing simulation should be avoided for arria 10 device. you can refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii5v3.pdf page 1-2.
What you can do is the following:
1) make sure you written the correct constrain in the sdc.
2) timing is close in the timing analyzer
3) signal tap on those failure path
Thanks,
VenkateshSatharPoint 1 and 2 i am already doing.
Regarding point 3 I already told that all the paths i Can't monitor in my design in signal tap as there as so many. Main thing is that The paths which are failing in real time are not even shown as failed in timing analyzer.
