Forum Discussion

VenkateshSathar's avatar
VenkateshSathar
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

not able to generate sdo for arria 10 soc for post-synthesis timing simulation

There is a standard procedure mentioned in so many places/links to do timing simualtion for any project using modelsim from quartus which is called as gate-level simulation also. I followed that and...
VenkateshSathar's avatar
VenkateshSathar
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Yeah I can see Arria 10 is not there in support list. is there any way to see timining simulation then still...? because in hardware i see really weird outputs. In TimeQuestAnalyser It didn't have any problems with the nets that I am seeing real time where the problem is there. It will be really tough to solve by seeing everything after testing in hardware. can you suggest any simple approaches to solve this problems of timing..? First thing is I am following design standards already for higher clock as mentioned in the following training.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/simulation/modelsim/exm-timing-verilog-msaltera.html

apart from this can you help me in any other way?