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VenkateshSathar's avatar
VenkateshSathar
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

not able to generate sdo for arria 10 soc for post-synthesis timing simulation

There is a standard procedure mentioned in so many places/links to do timing simualtion for any project using modelsim from quartus which is called as gate-level simulation also. I followed that and...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Can you attached your

1) *.sdc files

2)top_level.v files

3) Timing report.rprt files

for us to have a look? Let's review the *.sdc before we proceed further.

VenkateshSathar's avatar
VenkateshSathar
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

yeah. now i could able to see the failing paths in setup time by changing the default tcl commands which generates for only 10 paths to some 100000 paths where as in histogram failures are that many. IN that some are related to our application and seen it and changed the codes and in hardware it worked for 160MHz clock and 100MHz also. Now the same code I am changing the clock to 200MHz and now some other timing path fails and even i give latency etc also not getting corrected for Fast 900mv 100C model. Can you suggest something for how to proceed for this really high frequency clock where as slack is not reducing.