Forum Discussion
VenkateshSathar
Occasional Contributor
Occasional Contributornot able to generate sdo for arria 10 soc for post-synthesis timing simulation
There is a standard procedure mentioned in so many places/links to do timing simualtion for any project using modelsim from quartus which is called as gate-level simulation also. I followed that and...
KennyT_altera
Super Contributor
Super ContributorThey are few method to close the timing. But have to understand how your design work.
Since you are new on Timing Analyzer, you may have to refer to the module below:
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html
Click on the follow on courses for the timing training,
After understanding the courses, you can get better picture what you can do to do timing closure.
