Occasional Contributor
Super ContributorCan provide more specific failure symptom? Without know what are the failure on your hardware, would be hard to provide advice.
Does your gate level simulation show the expected value? Even though the gate level simulation does not use .sdo but it still use the fitter netlist to do the simulation.
Occasional Contributoryeah it is showing the expected values only after using .vho files for vhdl gate level simulation. For example , the problem is like i have an array where based on the input data and index it get accumulated and stored in an data array. Now the input data is fine and index is fine. but the data output read from array is not as expected in hardware when seeing in signal tap. This time best thing is to monitor that array also so that each time accumulating properly or not we will know. but that array is too big that we can do signal tap on that. still i just monitored some index of the array and those are fine. I want to monitor all then only we can know where the problem is happening and then we can correct. this kind of things in timining simulation when monitoring all signals very easy but in hardware somewhat tough like I told the case.
