Altera_Forum
Honored Contributor
Honored ContributormSGDMA response FIFO stucks if receives 256...512 bytes
I use Quartus II 64-Bit Version 15.02 Build 153
mSGDMA is used in ST to MM mode http://www.alteraforum.com/forum/attachment.php?attachmentid=11724&stc=1 in the Control register set bits DESCRIPTOR_CONTROL_GO_MASKDESCRIPTOR_CONTROL_ERROR_IRQ_MASK DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK DESCRIPTOR_CONTROL_END_ON_EOP_MASK Transfer length is 8192 1) ST source generate packets 100...248 , bytes with controlled period reset mSGDMA push descriptor ST generates packet read response in FIFO read data OK 1) ST source generate packets 256...512 , bytes with controlled period reset mSGDMA push descriptor ST generates packet response fill level is incremented read response in FIFO - response fill level is not decremented, "response FIFO is empty" is 0 data is correct push descriptor ST generates packet response fill level is incremented read response in FIFO - response fill level is not decremented, "response FIFO is empty" is 0 data is correct mSGDMA receives next portion of data, but response FIFO is stucks Have anybody thought on solving this trouble?
