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Altera_Forum
Honored Contributor
10 years agomSGDMA response FIFO stucks if receives 256...512 bytes
I use Quartus II 64-Bit Version 15.02 Build 153 mSGDMA is used in ST to MM mode http://www.alteraforum.com/forum/attachment.php?attachmentid=11724&stc=1 in the Control register set bits DES...
Altera_Forum
Honored Contributor
10 years agoIt should be high or the start of packet will be ignored. You should then investigate the reason why the DMA doesn't work with this setting. Be sure to check for the ready signal too, you shouldn't move to the next word as long as it is low. Which readyLatency did you set on your source interface?