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Altera_Forum
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10 years ago

mSGDMA response FIFO stucks if receives 256...512 bytes

I use Quartus II 64-Bit Version 15.02 Build 153 mSGDMA is used in ST to MM mode http://www.alteraforum.com/forum/attachment.php?attachmentid=11724&stc=1 in the Control register set bits DES...
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Altera_Forum
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10 years ago

There is something in fact, it looks like the read signal is low during your start of packet. Looking back at the other figures, I see that valid is also low each time you have a start of packet, making it not recognizes by the stream sink. That could be what makes the DMA behave strangely. Do you know why the valid signal gets low?