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designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

LVDS SERDES IP no DPA lock in simulation

Hi,

I am trying to simulate an LVDS SERDES IP but don't seem to get DPA lock and with that never any data output. I am simulating with ModelSim Intel FPGA starter edition 2020.3.

IP Settings:

- Functional mode: RX DPA-FIFO

- Number of channels: 16

- Data rate: 1352.0 Mbps

- SERDES factor: 8

The data clock is running at 676 MHz and data is changing on both clock edges. The input data is toggling so there are plenty of edges provided on the input side. rx_fifo_reset is low for all channels and rx_dpa_reset starts out high but gets removed (goes low) when pll_lock goes high. Bit slip control is enabled but hardcoded to 0 for all channels.

The output clock rx_coreclock stabilizes and pll_locked goes high after about 600 ns but even after 4 us simulation time non of the channels rx_dpa_locked outputs go high.

Any help is greatly appreciated.

Thanks!

  • designEngineer's avatar
    designEngineer
    5 years ago

    I figured out what the issue was:

    I used the example design simulation as a comparison and eventually saw that the example locks only after over 8 us. This seems way longer than what the lock time specification in the device datasheet is specifying.

    I then ran my own simulation for that long (before I had only run it up to 4 us as according to the lock time specification that is way more than should be needed) and it does also lock.

    I am posting this in case someone else ever runs into this issue.

    Thanks for the help along the way.

17 Replies

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hello,

    May I know your OPN and which version of Quartus are you using?

    Thank you.

    • designEngineer's avatar
      designEngineer
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      I am using Quartus Pro 20.3.0.158 but Quartus is only used to generate the IP (originally created in Quartus 19 but upgraded with 20.3.0.158) the issue is in ModelSim Intel FPGA starter edition 2020.3.

      I am not sure what OPN stands for.

      Thanks.

      • AminT_Intel's avatar
        AminT_Intel
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        Hello,

        OPN is Ordering Part Number. Please provide me your OPN so I can help you further on your inquiry.

        Thank you.

    • designEngineer's avatar
      designEngineer
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      These are the libraries I am using if this helps:

      vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/altera_mf.v
      vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/mentor/cyclone10gx_atoms_ncrypt.v
      vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/cyclone10gx_atoms.v
      vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/altera_lnsim.sv

      And these are the modules I am compiling for simulation:

      vlog -work work ../src/ip/dpaSerdes/altera_lvds_core20_191/synth/altera_lvds_core20_pll.v
      vlog -sv -work work ../src/ip/dpaSerdes/altera_lvds_core20_191/synth/altera_lvds_core20.sv
      vlog -sv -work work ../src/ip/dpaSerdes/altera_lvds_core20_191/synth/dpaSerdes_altera_lvds_core20_191_qxd6ljq.sv
      vlog -work work ../src/ip/dpaSerdes/altera_lvds_1950/synth/dpaSerdes_altera_lvds_1950_gu4p3ni.v
      vlog -work work ../src/ip/dpaSerdes/synth/dpaSerdes.v

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hello,

    I will need to clarify your problem statement. Does the DPA lock not available from the beginning or after after 4 us? It seemed like from your problem statement that we should be expecting DPA lock if you are using DPA mode.

    Can you please put your specification on your first comment to LVDS SERDES IP and run 'Generate Example Design' and let me know what you found.

    Screenshots from your end about your issue will also be helpful for me to assist you.

    In the meantime, you can also refer to our LVDS SERDES IP Guide from this link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf

    Thank you,

    Amin

    • designEngineer's avatar
      designEngineer
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      As stated in my first comment, DPA lock does NOT go high EVER, not at the beginning and still not after 4 us simulation time.

      Have you run the simulation I provided at all? The reason I provided it was so you can re-create the issue on your end and help. You can see the issue described clearly in there.

      I have already reviewed the LVDS SERDES IP Guide and am following the design recommendations.

      Attached is a screenshot of my simulation that shows that non of the serdes channels ever get DPA lock even though the data lines are all constantly toggling.

      If you can PLEASE take a look at the simulation and help me understand why DPA lock never happens I would greatly appreciate it.

      I have also attached the result of running generate example design hoping this helps.

      Thank you!