Forum Discussion
LVDS SERDES IP no DPA lock in simulation
- 5 years ago
I figured out what the issue was:
I used the example design simulation as a comparison and eventually saw that the example locks only after over 8 us. This seems way longer than what the lock time specification in the device datasheet is specifying.
I then ran my own simulation for that long (before I had only run it up to 4 us as according to the lock time specification that is way more than should be needed) and it does also lock.
I am posting this in case someone else ever runs into this issue.
Thanks for the help along the way.
Hello,
May I know your OPN and which version of Quartus are you using?
Thank you.
These are the libraries I am using if this helps:
vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/altera_mf.v
vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/mentor/cyclone10gx_atoms_ncrypt.v
vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/cyclone10gx_atoms.v
vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/altera_lnsim.sv
And these are the modules I am compiling for simulation:
vlog -work work ../src/ip/dpaSerdes/altera_lvds_core20_191/synth/altera_lvds_core20_pll.v
vlog -sv -work work ../src/ip/dpaSerdes/altera_lvds_core20_191/synth/altera_lvds_core20.sv
vlog -sv -work work ../src/ip/dpaSerdes/altera_lvds_core20_191/synth/dpaSerdes_altera_lvds_core20_191_qxd6ljq.sv
vlog -work work ../src/ip/dpaSerdes/altera_lvds_1950/synth/dpaSerdes_altera_lvds_1950_gu4p3ni.v
vlog -work work ../src/ip/dpaSerdes/synth/dpaSerdes.v