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designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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LVDS SERDES IP no DPA lock in simulation

Hi, I am trying to simulate an LVDS SERDES IP but don't seem to get DPA lock and with that never any data output. I am simulating with ModelSim Intel FPGA starter edition 2020.3. IP Settings: -...
  • designEngineer's avatar
    designEngineer
    5 years ago

    I figured out what the issue was:

    I used the example design simulation as a comparison and eventually saw that the example locks only after over 8 us. This seems way longer than what the lock time specification in the device datasheet is specifying.

    I then ran my own simulation for that long (before I had only run it up to 4 us as according to the lock time specification that is way more than should be needed) and it does also lock.

    I am posting this in case someone else ever runs into this issue.

    Thanks for the help along the way.

AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hello,

May I know your OPN and which version of Quartus are you using?

Thank you.

  • designEngineer's avatar
    designEngineer
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    I am using Quartus Pro 20.3.0.158 but Quartus is only used to generate the IP (originally created in Quartus 19 but upgraded with 20.3.0.158) the issue is in ModelSim Intel FPGA starter edition 2020.3.

    I am not sure what OPN stands for.

    Thanks.

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hello,

      OPN is Ordering Part Number. Please provide me your OPN so I can help you further on your inquiry.

      Thank you.

      • designEngineer's avatar
        designEngineer
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        Cyclone 10 GX: 10CX085YU484E5G

  • designEngineer's avatar
    designEngineer
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    These are the libraries I am using if this helps:

    vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/altera_mf.v
    vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/mentor/cyclone10gx_atoms_ncrypt.v
    vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/cyclone10gx_atoms.v
    vlog -sv -work altera C:/intelFPGA_pro/20.3/quartus/eda/sim_lib/altera_lnsim.sv

    And these are the modules I am compiling for simulation:

    vlog -work work ../src/ip/dpaSerdes/altera_lvds_core20_191/synth/altera_lvds_core20_pll.v
    vlog -sv -work work ../src/ip/dpaSerdes/altera_lvds_core20_191/synth/altera_lvds_core20.sv
    vlog -sv -work work ../src/ip/dpaSerdes/altera_lvds_core20_191/synth/dpaSerdes_altera_lvds_core20_191_qxd6ljq.sv
    vlog -work work ../src/ip/dpaSerdes/altera_lvds_1950/synth/dpaSerdes_altera_lvds_1950_gu4p3ni.v
    vlog -work work ../src/ip/dpaSerdes/synth/dpaSerdes.v