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designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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LVDS SERDES IP no DPA lock in simulation

Hi, I am trying to simulate an LVDS SERDES IP but don't seem to get DPA lock and with that never any data output. I am simulating with ModelSim Intel FPGA starter edition 2020.3. IP Settings: -...
  • designEngineer's avatar
    designEngineer
    5 years ago

    I figured out what the issue was:

    I used the example design simulation as a comparison and eventually saw that the example locks only after over 8 us. This seems way longer than what the lock time specification in the device datasheet is specifying.

    I then ran my own simulation for that long (before I had only run it up to 4 us as according to the lock time specification that is way more than should be needed) and it does also lock.

    I am posting this in case someone else ever runs into this issue.

    Thanks for the help along the way.

designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I just realized you may mean that when you run the simulation you don't get waveform data for the signal rx_dpa_locked. I don't know why this would be when I run the simulation I do get data for that signal but it is always low. See attached screenshot.

designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I figured out what the issue was:

I used the example design simulation as a comparison and eventually saw that the example locks only after over 8 us. This seems way longer than what the lock time specification in the device datasheet is specifying.

I then ran my own simulation for that long (before I had only run it up to 4 us as according to the lock time specification that is way more than should be needed) and it does also lock.

I am posting this in case someone else ever runs into this issue.

Thanks for the help along the way.