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AKhel1
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6 years ago

Issues using ST-Avalon on Stratix 10 MX development Kit

Hello,

I am porting an endpoint PCIe IP on my Stratix 10 MX development kit (1SM21BHU2F53E1VG) and I have some issues.

When using a test IP (xillybus) with ST-Avalon PCIE gen2 x8 and a correct pin assignement tooked from the exemple design provided wih the board I got this error messages in Fitter step:

Error(16400): Transceiver channel data signal < pcie_tx[0] > is assigned to pin < PIN_BH45 >, but the specified pin is not compatible with the data signal. Assign the specified data signal to pin < PIN_BL47 >.

Error(16400): Transceiver channel data signal < pcie_tx[1] > is assigned to pin < PIN_BJ47 >, but the specified pin is not compatible with the data signal. Assign the specified data signal to pin < PIN_BK49 >.

Error(16400): Transceiver channel data signal < pcie_tx[2] > is assigned to pin < PIN_BG47 >, but the specified pin is not compatible with the data signal. Assign the specified data signal to pin < PIN_BH49 >.

...

Error(16400): Transceiver channel data signal < pcie_tx[15] > is assigned to pin < PIN_AP45 >, but the specified pin is not compatible with the data signal. Assign the specified data signal to pin < PIN_AR51 >.

Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.

When I remove the PCIe TX assignement I get this error message:

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error(175020): The Fitter cannot place logic pin in region (3, 30) to (3, 31), to which it is constrained, because there are no valid locations in the region for logic of this type.

Error(16234): No legal location could be found out of 2 considered location(s). Reasons why each location could not be used are summarized below:

Error(184016): There were not enough differential input pin locations available (2 locations affected)

I attached the project if some one want to try.

Thanks a lot for your help

Best regards

Amine

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