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AKhel1
New Contributor
New ContributorIssues using ST-Avalon on Stratix 10 MX development Kit
Hello, I am porting an endpoint PCIe IP on my Stratix 10 MX development kit (1SM21BHU2F53E1VG) and I have some issues. When using a test IP (xillybus) with ST-Avalon PCIE gen2 x8 and a correct pin...
AKhel1New Contributor
New ContributorThank you :-)
This documentation need a correction then (page 31, 32 and 33): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-intel-s10-mx-devl-kit.pdf
Can you tell me also please what reset do I need to use for PCIe EP because I have the same problem ...
