New Contributor
New ContributorHello, Thank you for your answer.
The problem is the PIN_BL47 is for RX PCIe signal, not the TX, and it is the same as defined in the assignment of the example design qts_pcie_ep of the board and in the user guide ...
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-intel-s10-mx-devl-kit.pdf
It's maybe a constraint to add or something?
I recompiled the project that I attached to be sure, and it stops in the Fitter step. Maybe it's due to the Quartus version, I use the Quartus Prime Pro 19.4 which one do you use for your compilation?
I didn't make a lot of modifications, I just change the FPGA to the one I have, regenerate ST-Avalon and reset release IP and change the assignments to the correct one for my board.
Yes, the design was made for a different board (also a stratix 10). I can send you the original version of the project if it help?
