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AKhel1's avatar
AKhel1
Icon for New Contributor rankNew Contributor
6 years ago

Issues using ST-Avalon on Stratix 10 MX development Kit

Hello, I am porting an endpoint PCIe IP on my Stratix 10 MX development kit (1SM21BHU2F53E1VG) and I have some issues. When using a test IP (xillybus) with ST-Avalon PCIE gen2 x8 and a correct pin...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Noted.

What problem with the reset? I will suggest just follow the Quartus auto fit. Eg, compile the example design without location assignment and see it assign the rest to which pin. If you need further help, I hope you can create a new thread for this. It can help every single issue is track under independent thread. Ease the other to search if they are facing same issue.