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AKhel1
New Contributor
6 years agoIssues using ST-Avalon on Stratix 10 MX development Kit
Hello, I am porting an endpoint PCIe IP on my Stratix 10 MX development kit (1SM21BHU2F53E1VG) and I have some issues. When using a test IP (xillybus) with ST-Avalon PCIE gen2 x8 and a correct pin...
AKhel1
New Contributor
6 years agoI generate the example design and it compiles well, then I added the pin locations and I got the same error message (16400) then I permute RX and TX pin location and the design compile well. Is it correct to permute the TX and RX location ? in the example design of the board and in the documentation they didn't permute ... how PCIe would work if the TX became an RX and the RX a TX?
I also tried to permute the TX and RX in my original design, now I have only the Error(14566) and after