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AKhel1's avatar
AKhel1
Icon for New Contributor rankNew Contributor
6 years ago

Issues using ST-Avalon on Stratix 10 MX development Kit

Hello, I am porting an endpoint PCIe IP on my Stratix 10 MX development kit (1SM21BHU2F53E1VG) and I have some issues. When using a test IP (xillybus) with ST-Avalon PCIE gen2 x8 and a correct pin...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello, can you just follow the error message instruction to assign the pin accordingly? eg. Assign the specified data signal < pcie_tx[0] > to pin < PIN_BL47 >.

You need to follow the error message instruction to assign all 16 pins accordingly.

Anyway, from the attached design, I found it already compiled successful. Is there some misunderstanding here? I guess the design is working previously. but after you changed something and you get the fitter error? if yes, please clarify what change that you did. 😃