Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hie RamaMohan,

fast_sim does help to speed up the simulation related to analog functions to be shorter such as PLL locking,CDR locking and analogue calibration. Hence, its good you have enabled it.

However, you seem to be observing HiZ. This is typically caused by some of the IP's input ports floating upon starting simulation. I can't be certain this is the root cause, but firstly, please check if all you clocks are driven and resets have an initial value upon staring simulation.

Secondly, please check the FPGA is connected to the other end (if FPGA is endpoint, it is connected to a Root Port). This way the TX lines will observe a Rx and won't be showing HiZ for a long time.

Also do advice, which Arria 10 PCIe interface, configuration is being used (ex: AVMM Gen3x8 128bit) and which simulator is showing this behavior.

Regards,

Nathan

​

Hi Nathan,

Thanks for the reply. The HiZ being observed is at a point LTSSM on both (RC and EP) sides had proceeded to recovery speed state, which implies all the connectivity on serial interface side and input side is fine. We have physically verified the same in waveform as well.

Please refer to the attached snapshot of waveform showing A10 PCIe HIP signals which indicate this condition. The LTSSM state is also captured in the waveform.

We are using Arria10 PCIe Gen3, x8, 256bit is the configuration being used.

Thanks,

RamaMohan

​Hi Nathan,

Here is another snapshot that shows more simulation window where issue had occurred.

Thanks,

RamaMohan

Hie,

Could you advice if you are not able to achieve Lo at Gen3 after running simulation for longer period due to this issue?

i want to understand the LTSSM if its stuck at Recovery.Speed

Regards,

Nathan​

Hi Nathan,

Yes, RC model LTSSM is not able to proceed ​to L0 at Gen3 and Endpoint monitor goes out of sync due to this issue. The RC model is stuck in phase2 equalization after this.

But at Gen1 we are able to proceed to L0 state.

Thanks,

RamaMohan

​Hie,

I will to duplicate the issue in-house to debug further. Could you provide your simulation files (zipped). In the meanwhile, can you the following:

1. disable fast_sim
2. ensure following are disabled in your Arria 10 Hard IP for PCIe under Phy Characteristics tab:

• Enable Rx polarity inversion soft logic
• enable soft DFE controller IP

If not, please disable it and retry simulation.

Also change the Requested equalization Far end Tx Preset to Preset 0 if you are recompiling.

Regards,

Nathan

Hi Nathan,

Sure I'll check these parameters and try out with values proposed.

When you say zipped simulation files​, do you mean HIP files?

Also, lease let me know how can I share these with you?

Thanks,

RamaMohan

Hie,

I have another question which PCIe interface are you using. Are you using AVMM_SRIOV?

I mean your .tcl and library files (PCIe IP) that you are currently using to run simulation. There is an attach file icon in the forum, you could try using that.

Regards,

Nathan

​Is there an option to configure AVMM with SRIOV enabled? My interactions with Intel confirmed that this configuration wasn't available. So, is it fine if I attach just the .ip file?

Thanks,

RamaMohan

Hie,

Sorry, my mistake. I accidently typed AVMM_SRIOV instead of AVST-SRIOV. You are correct, we don't offer AVMM_SRIOV interface.

I needed to know which PCIe interface are you using currently, If you are using AVST-SRIO, then observed simulation is expected as the Intel-BFM don't support Gen3 Phase 2 and Phase 3 equalization.

Please advice accordingly.

Regards,

Nathan