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RamaMohan's avatar
RamaMohan
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7 years ago

Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hi, We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 F...
RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi Nathan,

Yes, RC model LTSSM is not able to proceed ​to L0 at Gen3 and Endpoint monitor goes out of sync due to this issue. The RC model is stuck in phase2 equalization after this.

But at Gen1 we are able to proceed to L0 state.

Thanks,

RamaMohan